Heterogeneous
multi-core system-on-chip (SoC) architectures will emerge as the major
computing platform to support applications in the infrastructure, mobile, and
sensor spaces. These platforms will be richly heterogeneous:
general-purpose processors are combined with many programmable and customizable
cores optimized for specific computation tasks (data-parallel, stream-computing
and specialized hardware accelerators. For many applications, particularly in
mobile and sensor uses, heterogeneity also results from combining digital
hardware with RF/AMS subsystems to support wireless communication and
interaction with the physical world. These platforms will be highly parallel, because concurrency is the only way to achieve scalable, energy-efficient
performance. These platforms will be distributed systems: inter-core
synchronization and communication play major roles in design, validation,
performance, and cost. The combination of heterogeneity, parallelism and
distribution in future platforms poses many hard challenges. While designing
single components is important, the critical challenges are in integrating
components, offering run-time management of the resources they provide, and
programming the overall system under constrained power budgets.
The Platform Architectures theme
brings together ten researchers from nine leading US universities with a
broad mix of expertise needed to address several important questions:
·
How to cope with the complexity of designing future SoC platform architectures
by integrating many heterogeneous cores, including programmable cores,
configurable cores and RF/AMS components, under a limited power budget?
·
How to develop new abstractions and APIs at the interface between system
software and heterogeneous hardware that will be used to efficiently program
and manage these SoCs?
·
How to design scalable and power efficient on-chip interconnection fabrics
that support both high performance data transfers and efficient management
of the chip resources?
·
How to maintain scalable designs across technology generations when the counts
and types of heterogeneous cores are changing. How to exploit new interconnect
technologies like 3D, RF and optics?
This theme will include efforts in three clusters: rethinking platform
abstraction and architecture layers to enable power/performance-efficient
mappings of applications onto heterogeneous multi-core SoC platforms;
designing and managing non-processor (uncore) issues such as memory
hierarchies and interconnect; and research on technology drivers, modeling
support, and design methods, including automatic generation of RF/AMS
subsystems.
The overarching objective is to enable the realization of scalable platform
architectures that offer at least 100X gain in power/performance efficiency
with at least 10X productivity improvement over the next 8-12 years to meet the
computation, communication, and memory requirements of different applications
across a variety of heterogeneous multi-core SoC solutions. These will span from
the infrastructure segment with a 150W power budget to the mobile and sensor
segments with sub-1W power budgets.
