Scalable Parallel Programming for Multi-cores and Many-Cores
Verification-Guided Error Resilience
Speculatively Parallelizing Implicitly Parallel Programs on Commodity Hardware [ edit ]
GSRC Design Drivers - The Good and the Bad
Dynamic Management and Resource Allocation in CMPs: Lessons Learned and Looking Forward…
Reconfigurable Computing & Bayesian Networks [ edit ]
PetaBricks: Building Languages and Compilers for Multi-cores
Application-Aware SoftWareAnomalyTreatment(SWAT)of Hardware Faults [ edit ]
Core Pillar Accomplishments
Runtime Validation of Multi-Core Concurrency Semantics
Networks of Coupled Oscillators
GSRC 2009-2012 The Road Ahead
Stochastic Sensor Network-on-a- Chip
MuSyC - Center Overview - Sept 2009
Effective Scheduling at Large Scale
The StageNet Fabric for Constructing Resilient Multicore Systems [ edit ]
Communication-Based Design: A Three-Year Retrospective
Communication Modeling for System-Level Design
Overview of Contributions
TLM-based System Design and Verification
Performance- and Energy-aware Networks-on-Chip Optimization
Scalable Formal Verification for Complex Hardware and Concurrent Software
On-line Self-Test & Diagnostics for Robust Systems
Mapping Applications onto Manycore: From Speed-ups to Frameworks
State of the Center - 2009 GSRC Annual Symposium and Review
Application-aware Checking: Recent Progress
Exploring Alternative Models of Computation
Scalable and Resilient CMPs
Injection Locking Analysis and Efficient Coupled Oscillator Simulation
Success With The Implicitly Parallel Programming Model
The Core Theme
ERSA: Error Resilient System Architecture
Automated Reduced Order Model Generation for Nonlinear Systems
Brain-Machine Interfaces
Concurrent Systems Theme
Lithe: Enabling Efficient Composition of Parallel Libraries
Applying Recognition Techniques to Image Retrieval [ edit ]
Multiband RF-Interconnect for Reconfigurable Network-on-Chip Communications [ edit ]
Growing Up Resilient
GSRC 2009‐2012 -- The Road Ahead
State of the Center 2009 -- GSRC EAG Meeting
MuSyC and GSRC Collaborations
Experience in Parallelizing Implicitly Parallel Programs
Scalable Parallel Programming for Multi- and Many-Core Processors
PALLAS - Experience in performance programming of many-cores with emphasis on hight-level patterns and frameworks
StreamItand PetaBricks: Experience in Building Languages and Compilers for Multicores
Experiences in Video Processing Applications [ edit ]
Experience with Speculatively Parallelizing Implicitly ParallelPrograms using a Lightweight Software Transactional Memory [ edit ]
Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors
A Case for Integrated Processor-Cache Partitioningin Chip Multiprocessors
In-Network Coherence Filtering: Snoopy Coherence without Broadcasts [ edit ]
Rigel: An Architecture and Scalable Programming Interface for a 1000‐core Accelerator
Scalable Verification of Concurrent Software [ edit ]
Energy Efficient Multiprocessor Task Scheduling under Input-dependent Variation
Development of a Building Operating Platform [ edit ]
Run-time Energy Optimization for Networks-on-Chip
Progress on Analytical NoC Router Power and Area Modeling
End-to-End Flow Control in NoCs for Heterogeneous SoCs
ManiMOR: Model Reduction by Projection on Nonlinear Manifolds 2009/07/17
Analog Platform-Based Design
FTGen: An Automatic Fault Tree Generation Tool for the Design and Analysis of Fault Tolerant Architectures [ edit ]
Identifying critical instructions in programs
MetroII-ASPN Synthesis Flow Progress Update
Environment and Process Aware Low Power Wireless Systems
Low-cost Reliable NoCsThrough Degradable Components [ edit ]
MSWAT: Hardware Fault Detection and Diagnosis for Multicore Systems [ edit ]
A Microcontroller-Based Approach for Application-Aware Error Detectors
Modeling Yield, Cost, and Quality of a Spare-enhanced Multi-core Chip
Modeling Energy-Error Behavior for Stochastic Sensor Network-on-Chip Applications
Stochastic Sensor Network-on-a-Chip
On-chip Stochastic Communication and Beyond: Past, Present, and Future…
Ulta-Low Power Platforms for BMI
Brain-Machine Interfaces - From Health Care to New Trends on Information Technology [ edit ]
Coupled Oscillator Network Project Review
Towards Correctness-Constrained Execution for Processor Designs
Future Test Needs: A TI View
System Design in the Late- and Post-Silicon Eras
Texas Instruments & GSRC -- Markets for Electronics in the 21st Century [ edit ]
GSRC Workshop
Future of Architecture: Programmable Systems Architectures
Stochastic Computation
Ultra-Low Voltage Design for New Implantable Applications
Microscopic Wireless to Power Brain-Machine Interfaces
Emerging Approaches for Network-based Communication
Bio-Inspired Stochastic Computation
Ultra Low Power Programmable Platforms for Smart Grid and Broadband Communications – Are They Feasible?
Seeing the Future of Video [ edit ]
Concurrent Systems Theme -- Removing Parallel Application Roadblocks
On the Rules of Robust Design (and How to Break Them)
GSRC Design Drivers
GSRC -- Quo Vadis?
Integrated Test and Validation for Mixed-Signal/RF
Runtime Validation
Verification of SoC Designs: What's Next?
Verifying the FITness of Sequential Circuits
Statistical Prediction of Circuit Aging
Globally Optimized Robust Systems On-line Test & Application-Aware Resilience
Rethinking Resilience: Health Monitoring and Diagnostics [ edit ]
Wearout: Predicting, Monitoring, and Responding
Digital-assisted Analog/RF Validation and Testing: Case studies of Image-Reject Receivers and Pipeline ADCs
SSNOC/Coupled Oscillator Test Chip Progress Report
Information Propagation in Ring Oscillator Network
Soft NMR
On-Chip Stochastic Communication
Modeling Energy-Error Behavior for Stochastic Sensor Network-on-Chip Applications [ edit ]
Synergies with FENA
Update from CORE theme
ERSA -- Error Resilient System Architecture for RMS Applications
Portable Parallel Programming with MCUDA
Content Based Image Retrieval on Mobile Devices
Monitoring Atomicity in Concurrent Programs [ edit ]
Trace-Driven Verification of Multi-Threaded Programs [ edit ]
COSI: COmmunication Synthesis Infrastructure
Transaction Level Design and Verification
Synthesis of Application Specific Processor Network (ASPN) Exploiting execution time variation for energy minimization
Communication Modeling for Improved System-Level Design
Flit-Buffer Flow Control for Networks-on-Chip [ edit ]
State of the Center
Energy Optimization for NoCs
Alternative Computational Models
Metro II simulation analysis using an UMTS case study [ edit ]
Resilient Results
Stochastic Networked Computation
Sparing and Routing for Performance Variability and Fault Tolerance
Engineering Trust with Semantic Guardians
Networks of Oscillators for Synchronization
Concurrent Systems Theme -- Removing parallel application roadblocks.
SWAT: Hardware Reliability by Treating Software Anomalies [ edit ]
Imperfection-Immune Carbon Nanotube VLSI
Voltage-Scalable Error Resilient Microarchitecture
Runtime Validation of Concurrency Support for Multi-Core Processors
Coded Boolean Circuits
Application Aware Wireless Systems: Adaptive Hardware and Software
Interfacing the Brain: Interfacing the Brain: Current Trends in Neural Engineering
Concurrent Systems Theme -- Removing parallel application roadblocks
Adaptive Set Pinning: Managing Shared Caches in CMPs
Task Management for Cache Incoherent Accelerator Architectures
Research problems in embedded distributed systems
Chips as Distributed Systems
Wireless Sensor Networks in Distributed Systems
eWorkshop on Distributed Systems
Large Scale Distributed Systems - Building & Aerospace Applications
New Automotive DNA [ edit ]
Neuro-inspired and Neuro-applied Workshop
The Challenges Moving from Biomedical Appliances to Neuro-Inspired Computing
Insect Leg Sense Organs and Their Functions [ edit ]
Neuro-Inspired and Neuro-Applied Computing [ edit ]
The mammalian thalamocortical network: a "simple" circuit to study "complex" activities? [ edit ]
Biologically Inspired Beamforming
The Future of Data Centers - GSRC Workshop
E-Workshop on the Future of Data Centers - GSRC Overview
Rethinking server design for the ensemble - Server and rack efficiency [ edit ]
Thermal Issues for Future Data Centers - Challenges, Innovative Solutions [ edit ]
Heterogeneity and Scale -- Challenges for Resource Management [ edit ]
Storage Class Memory and the data center of the future [ edit ]
Networking and Consolidation in Data-Center [ edit ]
Road to Green Metrics – from the Storage Industry Perspective [ edit ]
Post-Silicon Validation of Multicore Chips Using Dynamic Verification
Design Visibility in Post Silicon Verification
The Challenges of Correlating Silicon and Models in High Variability CMOS Processes
Workshop Announcement & Agenda
Post-Silicon Validation Workshop
Post-Si Validation Experience: History, Trends, and Challenges
Directable Functional Exercisers
Lightweight, Scalable Tools for Hardware Validation
Runtime Pipeline Checking: Seatbelts for Your CPU
Runtime Validation of Transaction Memory Systems
GSRC - Quo Vadis?
Stochastic Communications
Parallelizing LVCSR on GPU [ edit ]
Chip Life Management Through Sensor and in situ Monitoring of Reliability Degradation
On-Line Circuit Reliability Monitoring
CUDA for x86 Multicore Processors
Mutations for Coverage and Fault Tolerance
Virtual Tree Coherence: Leveraging In-Network Multicast Trees for Ordering Cache Coherence [ edit ]
Enabling CPU/Accelerator Hybrid Architectures [ edit ]
Towards High-performance Dynamic Parallelism Management & Emulation for Power/Thermal Studies of CMP Architectures
A Helper Thread Based EDP Reduction Scheme for Adapting Application Execution in CMPs [ edit ]
Latency-Insensitive Design and Communication-Synthesis
Architecture Implications of 3D Integration and Other Technologies [ edit ]
Pattern Identification and Extraction in Behavioral Synthesis and ASIP Designs
A Biologist's Need for Computation -- Agony & Ecstasy [ edit ]
A Formal Framework for Validating Application-aware Error Detectors
Oscillator Networks, their Properties and Potential Applications
Networked Computation
Exploring Unreliable Technology Scaling for High Performance Systems
Coding for High-Defect Fabrics
Imperfection-Immune CNFET Circuits
A Map Reduce Framework for Programming GPUs
Stochastic Communication
Architectural Support to Eliminate Barriers in Parallel Programming and Automatic Parallelization [ edit ]
Reliability-Aware Design for Multi-Processor Systems on Chip
TLM Functional Verification and Interface to Metro-II
CRISTA: An Integrated Technique for Voltage-overscaling and Error Resiliency
Virtualization & Machine Learning: A New Approach to Server HA
Sustaining Error Resiliency: The IBM POWER6TM Microprocessor [ edit ]
Rethinking Resilience
Stochastic Design and Analysis of Networks-on-Chip
Communication Modeling for System Level Design
Using Defect-Map Knowledge for More Efficient Coding [ edit ]
Collaborative Radio Project Update [ edit ]
Perturbation Based Computing
Imperfection-Immune Carbon Nanotube FET Circuits
MetroSPICE++ Core Update
Core Theme Overview and Design Flow
System-Level Modeling II (Routers)
MC-Sim: an Efficient Simulation Tool for Heterogeneous Multi-core Systems [ edit ]
Energy-Aware Design for 1000 Cores: Exploiting VFIs for NoC-Based Systems [ edit ]
TLM Verification Tool and Interface to Metro-II
Synthesis of Reconfigurable High-Performance Multicore Systems
Modeling and Metrics Initiative: In Search of Common Ground
Metrics for Architecture-Level Lifetime Reliability Analysis [ edit ]
Models and Metrics for Test
SymPLFIED: Symbolic Program Level Fault Injection and Error Detection Framework
Reliability Modeling and Simulation for Nanoscale Design
NBTI Induced Performance Degradation in Logic and Memory Circuits: How Effectively Can We Approach a Reliability Solution? [ edit ]
Specification Based Testing vs. Fault Based Testing: Dilemma for Low Cost Testing of Mixed- Signal and RF Circuits
Resilient System Design Theme: Surviving In the Silicon Jungle
Exploiting the Synergy Between Fault Tolerance, Manufacturing Test and Debug [ edit ]
The Importance of Test [ edit ]
CrashTest: Resiliency Analysis Framework [ edit ]
Workloads of the Future
Future Workloads for Designing Future Computers
Print Workload [ edit ]
NERSC Workload Analysis [ edit ]
Where are Internet workloads going? [ edit ]
Workloads of the Future: "Mobility, Community, Serendipity" [ edit ]
Connecting the Unconnected: the networking challenge
Remarks on Workloads of the Future [ edit ]
High Performance Buildings (Systems) (...and Power...) Challenges for Embedded Systems & Enabling Opprotunities for GSRC
GSRC Workshop: Workloads of the Future [ edit ]
NVIDIA GPU Computing [ edit ]
Theoretical Foundations (Alternatives subtheme)
Communication Fabrics
Exploring Network Properties of Oscillators Slides in PDF
Embedded Computer Vision: Challenges and Opportunities Slides in PDF
Accelerating Support Vector Machine Training and Classification Slides in PDF
Spatially Aware Services Applications on Future Generation of Handsets Slides in PDF
Star Challenge -- A real-world computer vision task which requires large amounts of computation power Slides in PDF
Domain-Specific Power-Efficient Computing Slides in PDF
Hard Threads and Liquid Threads: Managing Processing Resources in a Manycore System Slides in PDF
Performance, Energy, and Fault-tolerance Issues in NoC Design Slides in PDF
Synthesis of Reconfigurable High High-Performance Multicore Systems
