Overview of Contributions
Multiband RF-Interconnect for Reconfigurable Network-on-Chip Communications [ edit ]
Efficient Test Strategies for Digitally-Calibrated Designs: An ADC Case Study
Growing Up Resilient
Exploiting Asymmetric Parallelism with DSWP
Performance- and Energy-aware Networks-on-Chip Optimization
Scalable Parallel Programming for Multi-cores and Many-Cores
FCUDA: Compilation of CUDA kernels onto FPGA
Verification-Guided Error Resilience
ACES: Application-specific Cycle Elimination and Splitting for Deadlock-free Routing on Irregular NoC
On-line Self-Test & Diagnostics for Robust Systems
Speculatively Parallelizing Implicitly Parallel Programs on Commodity Hardware [ edit ]
Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in CMPs
GSRC Design Drivers - The Good and the Bad
Phoenix Rebirth: Scalable MapReduce on a NUMA System [ edit ]
Alternate Approach to SSNOC: Outlier Detection
Dynamic Management and Resource Allocation in CMPs: Lessons Learned and Looking Forward…
Scheduling for Power, Performance and Reliability
Reconfigurable Computing & Bayesian Networks [ edit ]
Scalable Process Address Space Management
Stochastic Sensor NOC
PetaBricks: Building Languages and Compilers for Multi-cores
Using Concurrency to Check Concurrency: Checking Serializability in Software Transactional Memory
Application-Aware SoftWareAnomalyTreatment(SWAT)of Hardware Faults [ edit ]
Parallelizing Implicitly Parallel Applications for Commodity Multicore Systems [ edit ]
Soft NMR
Core Pillar Accomplishments
Error-Resilient Low-Power Viterbi Decoders
Runtime Validation of Multi-Core Concurrency Semantics
A MEMS Filter Bank Receiver [ edit ]
Development of a Building Operating Platform [ edit ]
Networks of Coupled Oscillators
Low Power Robust System Design through Unequal Error Protection, Voltage Over-Scaling & Adaptive Quality Tuning [ edit ]
GSRC 2009-2012 The Road Ahead
CMP Architectures with Emerging 3D and Non-Volatile Memory Technologies
Scalable HMM based Inference Engine in Large Vocabulary Continuous Speech Recognition
Stochastic Sensor Network-on-a- Chip
Improved On-Chip Router Performance, Power and Area Modeling
MuSyC - Center Overview - Sept 2009
HADOOP: How About, 'Don't Overburden Our Powerplants?' [ edit ]
YENSS: Fast Estimation of SRAM/Oscillator Yield Due to Parameter Variability
Effective Scheduling at Large Scale
Application Aware SoftWare Anomaly Treatment [ edit ]
Low Overhead Time-Multiplexed Online Checking: A Case Study of an H.264 Decoder
ManiMOR: Nonlinear Model Order Reduction via Projection on Nonlinear Manifolds
MSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicore [ edit ]
Damascene: Highly Parallel Image Contour Detection [ edit ]
Gen-Adler: Generalized Adler Equation
Digitally Assisted Built-in Tuning of RF Systems
Cache Sharing Aware Computation Distribution and Scheduling for Multicore Systems
Coupled Oscillator Simulation
Distributed Flit-Buffer Flow Control for Networks-on-Chip [ edit ]
FTGen: An Automatic Fault Tree Generation Tool for the Design and Analysis of Fault Tolerant Architectures
Living with Uncertainty: The Quest for Fault-Tolerant Networks-on-Chip Communication Protocols
CTC End-to-End Flow Control for Networks on Chip
TLM-based System Design and Verification
BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient Search
Verification Guided Error Resilience
Specification and Encoding of Transaction Interaction Properties in Transaction-Based Models
Scalable Formal Verification for Complex Hardware and Concurrent Software
CASP: Concurrent Autonomous Chip Self-Test and Diagonstics Using Stored Test Patterns [ edit ]
Integrated Processor-Cache Partitioning in CMPs
Brain Machine Interfaces
Mapping Applications onto Manycore: From Speed-ups to Frameworks
State of the Center - 2009 GSRC Annual Symposium and Review
Sense Amplifier-based Pass Transistor Logic
Run-Time Energy Optimization for Networks-on-Chip
Application-aware Checking: Recent Progress
ADAPT: An Automated Doubly Adaptive Performance Modeling Tool for GPU Architectures
Exploring Alternative Models of Computation
Analog Platform-based Design
StageNet: An Adaptive CMP System for Wearout Tolerant Computing [ edit ]
Scalable and Resilient CMPs
Modeling Yield, Cost, and Quality of a Spare-enhanced Multi-core Chip
Injection Locking Analysis and Efficient Coupled Oscillator Simulation
PetaBricks: A Language and Compiler for Algorithmic Choice [ edit ]
Error Resilient System Architecture (ERSA)
Success With The Implicitly Parallel Programming Model
Efficient Coding Techniques for Defect Tolerance in Future Nano-Circuits
The Core Theme
Connectivity Brokerage: From Coexistence to Collaboration [ edit ]
The StageNet Fabric for Constructing Resilient Multicore Systems [ edit ]
ERSA: Error Resilient System Architecture
Modeling Energy-Error Behavior for Stochastic Sensor Network-on-Chip Applications
Automated Reduced Order Model Generation for Nonlinear Systems
Joint Resource Management for QoS in Many-Core Chips [ edit ]
Communication-Based Design: A Three-Year Retrospective
Brain-Machine Interfaces
Fine-Grained Decay-Based Capacity Management For Shared CMP Caches
Concurrent Systems Theme
An Approach to Energy-Performance-Reliability Tradeoff for On-Chip Network Synchronizations
Communication Modeling for System-Level Design
Lithe: Enabling Efficient Composition of Parallel Libraries
System-level ISA
Applying Recognition Techniques to Image Retrieval [ edit ]
Identifying critical instructions in programs
GSRC 2009‐2012 -- The Road Ahead
State of the Center 2009 -- GSRC EAG Meeting
MuSyC and GSRC Collaborations
Experience in Parallelizing Implicitly Parallel Programs
Scalable Parallel Programming for Multi- and Many-Core Processors
PALLAS - Experience in performance programming of many-cores with emphasis on hight-level patterns and frameworks
StreamItand PetaBricks: Experience in Building Languages and Compilers for Multicores
Experiences in Video Processing Applications [ edit ]
Experience with Speculatively Parallelizing Implicitly ParallelPrograms using a Lightweight Software Transactional Memory [ edit ]
A Case for Integrated Processor-Cache Partitioningin Chip Multiprocessors
In-Network Coherence Filtering: Snoopy Coherence without Broadcasts [ edit ]
Rigel: An Architecture and Scalable Programming Interface for a 1000‐core Accelerator
Scalable Verification of Concurrent Software [ edit ]
Energy Efficient Multiprocessor Task Scheduling under Input-dependent Variation
Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors
FTGen: An Automatic Fault Tree Generation Tool for the Design and Analysis of Fault Tolerant Architectures [ edit ]
MetroII-ASPN Synthesis Flow Progress Update
Run-time Energy Optimization for Networks-on-Chip
Progress on Analytical NoC Router Power and Area Modeling
End-to-End Flow Control in NoCs for Heterogeneous SoCs
ManiMOR: Model Reduction by Projection on Nonlinear Manifolds 2009/07/17
Analog Platform-Based Design
Environment and Process Aware Low Power Wireless Systems
Low-cost Reliable NoCsThrough Degradable Components [ edit ]
MSWAT: Hardware Fault Detection and Diagnosis for Multicore Systems [ edit ]
A Microcontroller-Based Approach for Application-Aware Error Detectors
On-chip Stochastic Communication and Beyond: Past, Present, and Future…
Ulta-Low Power Platforms for BMI
Brain-Machine Interfaces - From Health Care to New Trends on Information Technology [ edit ]
Coupled Oscillator Network Project Review
Stochastic Sensor Network-on-a-Chip
Towards Correctness-Constrained Execution for Processor Designs
Yield and Cost Modeling of a Spare-Enhanced NoC
On the Rules of Robust Design (and How to Break Them)
Verfication Guided Error Resilience (VGER)
GSRC Design Drivers
Compiler-Driven Speculative Parallelization on Commercial HW
Connectivity Broker For Reliability in Wireless
GSRC -- Quo Vadis?
Pervasive Embedded System for Health Monitoring and Diagnosis
Variation Resilient Spin Torque Transfer MRAM [ edit ]
System Design in the Late- and Post-Silicon Eras
Texas Instruments & GSRC -- Markets for Electronics in the 21st Century [ edit ]
GSRC Workshop
Future of Architecture: Programmable Systems Architectures
Stochastic Computation
Ultra-Low Voltage Design for New Implantable Applications
Integrated Test and Validation for Mixed-Signal/RF
Microscopic Wireless to Power Brain-Machine Interfaces
Runtime Validation
Emerging Approaches for Network-based Communication
Verification of SoC Designs: What's Next?
Bio-Inspired Stochastic Computation
Future Test Needs: A TI View
Ultra Low Power Programmable Platforms for Smart Grid and Broadband Communications – Are They Feasible?
Application Specific Processor Network Synthesis
Seeing the Future of Video [ edit ]
ElastIC Based Network-on-Chip
An Approach to Model Order Reduction for Nonlinear Dynamical Systems in a General Nonlinear Projection Framework
Concurrent Systems Theme -- Removing Parallel Application Roadblocks
Oscillator Networks and Synchronization
Wearout: Predicting, Monitoring, and Responding
Digital-assisted Analog/RF Validation and Testing: Case studies of Image-Reject Receivers and Pipeline ADCs
Verifying the FITness of Sequential Circuits
Statistical Prediction of Circuit Aging
Globally Optimized Robust Systems On-line Test & Application-Aware Resilience
Rethinking Resilience: Health Monitoring and Diagnostics [ edit ]
SSNOC/Coupled Oscillator Test Chip Progress Report
Information Propagation in Ring Oscillator Network
On-Chip Stochastic Communication
Modeling Energy-Error Behavior for Stochastic Sensor Network-on-Chip Applications [ edit ]
Synergies with FENA
Update from CORE theme
ERSA -- Error Resilient System Architecture for RMS Applications
Semantics-Preserving Automatic Code Generation of Synchronous Reactive Communication [ edit ]
Concurrent Systems Theme -- Removing parallel application roadblocks.
Sparing and Routing for Performance Variability and Fault Tolerance
Adaptive Set Pinning: Managing: Managing Shared Caches in CMPs
Transaction Level Design and Verification
Extending Open Core Protocol to support System-Level Cache Coherence [ edit ]
FPGA Prototyping of Stochastic SNOC
Synthesis of Application Specific Processor Network (ASPN) Exploiting execution time variation for energy minimization
Toward Optimal Sound Reproduction: Closing the Acoustic Loop
Leveraging Local Intra-Core Information to Increase Global Performance in Block-Based Design of Systems-on-Chip
Unlocking the Potential of Automatic Parallelization
Communication Modeling for Improved System-Level Design
Modeling of Complex Bus Architectures: Enabling Heterogeneous Network Synthesis
Voltage-Scalable Error Resilient Microarchitecture
An End-to-end Approach for the Automatic Derivation of Application-Aware Error Detectors
Flit-Buffer Flow Control for Networks-on-Chip [ edit ]
State of the Center
SSNOC Test Chip in 90nm CMOS with Distributed Synchronization
Energy Optimization for NoCs
Alternative Computational Models
Application Aware Adaptation of Wireless Systems : Image Processing
Performance Analysis for On-Chip Stochastic Communication
Metro II simulation analysis using an UMTS case study [ edit ]
PriM: Modeling for Verification
Full-System Chip Multiprocessor Power Evaluations Using FPGA-Based Emulation
Resilient Results
Stochastic Networked Computation
Formal Verification of Microprocessors: One Step Closer to Hardware Designers
Runtime Validation of Hardware Transactional Memory Systems
Engineering Trust with Semantic Guardians
Networks of Oscillators for Synchronization
Automating Generation of Verification Tasks
SymPLFIED: Symbolic Program Level Fault Injection and Error Detection Framework [ edit ]
SWAT: Hardware Reliability by Treating Software Anomalies [ edit ]
Imperfection-Immune Carbon Nanotube VLSI
Partition Algorithms for Parallelizing Post-Layout Timing Optimization
Vicis: A High Reliability NoC Router
RAMP Blue: Architecture, Implementation and RDL [ edit ]
Communication Synthesis Infrastructure
Circuit Aging Analysis under NBTI Effect
Runtime Validation of Concurrency Support for Multi-Core Processors
RAMP Gold Outline Platform and Architecture [ edit ]
Coded Boolean Circuits
EVM Testing of Wireless OFDM Transceivers Using Intelligent Back-End Digital Signal Processing Algorithms
SWAT-Sim: Accurate Microarchitecture-Level Fault Models [ edit ]
Application Aware Wireless Systems: Adaptive Hardware and Software
RAMP Description Language RDL Overview and Timing [ edit ]
Interfacing the Brain: Interfacing the Brain: Current Trends in Neural Engineering
Fast SVM Training and Classification on a GPU
CoSMa: Post-Silicon Verification for Cache Coherence
The Cognitive Radio Test Bed [ edit ]
Design Paradigm for Low Power, Variation Resilient Systems using Adaptive Quality Modulation: Color Interpolation
Concurrent Systems Theme -- Removing parallel application roadblocks
A MEMS Filter Bank Receiver
SWAT: Hardware Reliability through Software Anomaly Treatment [ edit ]
Task Management for Cache Incoherent Accelerator Architectures
Adaptive Set Pinning: Managing Shared Caches in CMPs
Operating System Support for Parallel Applications on Manycore Platforms [ edit ]
Self-Healing Transceiver Design: Low Cost Built-in Test and Control Driven Simultaneous Tuning of Multiple Performance Metrics
Pattern-Based Behavioral Synthesis and ASIP Synthesis
MCjammer: Adaptive Verification for Multi-core Designs
Portable Parallel Programming with MCUDA
Digitally-Assisted Production Testing of a Digitally Calibrated RF Receiver
Guided Probabilistic Error Compensation for Voltage Overscaled Low-Power Digital Filters
ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration
Time-Multiplexed Online Checking: Resilient Design for Cost-Sensitive SoCs
Content Based Image Retrieval on Mobile Devices
Design Paradigm for Low Power, Variation Resilient Systems using Adaptive Quality Modulation
SRAM power optimization framework: a reliability perspective
Energy-Aware Design of Networks-on-Chip
Monitoring Atomicity in Concurrent Programs [ edit ]
CrashTest: a Fault Analysis Platform [ edit ]
Development, Management, and Deployment of Synthetic Biological Systems Using Standardized Parts [ edit ]
Trace-Driven Verification of Multi-Threaded Programs [ edit ]
CrashTest’ing SWAT [ edit ]
On-Line Circuit Reliability Monitoring
Adaptive Precision Arithmetic (APA) for Error Tolerant Applications
A Flexible 3D Communication Architecture for Media Mining Applications
A Cost Analysis Framework for Multi-core Systems with Spares [ edit ]
Data Parallel Large Vocabulary Continuous Speech Recognition on Graphics Processing Unit
COSI: COmmunication Synthesis Infrastructure
eWorkshop on Distributed Systems
Large Scale Distributed Systems - Building & Aerospace Applications
New Automotive DNA [ edit ]
Research problems in embedded distributed systems
Chips as Distributed Systems
Wireless Sensor Networks in Distributed Systems
Neuro-Inspired and Neuro-Applied Computing [ edit ]
The mammalian thalamocortical network: a "simple" circuit to study "complex" activities? [ edit ]
Biologically Inspired Beamforming
Neuro-inspired and Neuro-applied Workshop
The Challenges Moving from Biomedical Appliances to Neuro-Inspired Computing
Insect Leg Sense Organs and Their Functions [ edit ]
The Future of Data Centers - GSRC Workshop
E-Workshop on the Future of Data Centers - GSRC Overview
Rethinking server design for the ensemble - Server and rack efficiency [ edit ]
Thermal Issues for Future Data Centers - Challenges, Innovative Solutions [ edit ]
Heterogeneity and Scale -- Challenges for Resource Management [ edit ]
Storage Class Memory and the data center of the future [ edit ]
Networking and Consolidation in Data-Center [ edit ]
Road to Green Metrics – from the Storage Industry Perspective [ edit ]
Post-Silicon Validation Workshop
Post-Si Validation Experience: History, Trends, and Challenges
Directable Functional Exercisers
Lightweight, Scalable Tools for Hardware Validation
Runtime Pipeline Checking: Seatbelts for Your CPU
Runtime Validation of Transaction Memory Systems
Post-Silicon Validation of Multicore Chips Using Dynamic Verification
Design Visibility in Post Silicon Verification
The Challenges of Correlating Silicon and Models in High Variability CMOS Processes
Workshop Announcement & Agenda
GSRC - Quo Vadis?
Stochastic Communications
Parallelizing LVCSR on GPU [ edit ]
Chip Life Management Through Sensor and in situ Monitoring of Reliability Degradation
CUDA for x86 Multicore Processors
Mutations for Coverage and Fault Tolerance
Virtual Tree Coherence: Leveraging In-Network Multicast Trees for Ordering Cache Coherence [ edit ]
Enabling CPU/Accelerator Hybrid Architectures [ edit ]
Towards High-performance Dynamic Parallelism Management & Emulation for Power/Thermal Studies of CMP Architectures
A Helper Thread Based EDP Reduction Scheme for Adapting Application Execution in CMPs [ edit ]
CRISTA: An Integrated Technique for Voltage-overscaling and Error Resiliency
Virtualization & Machine Learning: A New Approach to Server HA
Sustaining Error Resiliency: The IBM POWER6TM Microprocessor [ edit ]
Rethinking Resilience
Stochastic Design and Analysis of Networks-on-Chip
Communication Modeling for System Level Design
Latency-Insensitive Design and Communication-Synthesis
Architecture Implications of 3D Integration and Other Technologies [ edit ]
Pattern Identification and Extraction in Behavioral Synthesis and ASIP Designs
A Biologist's Need for Computation -- Agony & Ecstasy [ edit ]
A Formal Framework for Validating Application-aware Error Detectors
Oscillator Networks, their Properties and Potential Applications
Networked Computation
Exploring Unreliable Technology Scaling for High Performance Systems
Coding for High-Defect Fabrics
Imperfection-Immune CNFET Circuits
A Map Reduce Framework for Programming GPUs
Stochastic Communication
Architectural Support to Eliminate Barriers in Parallel Programming and Automatic Parallelization [ edit ]
Reliability-Aware Design for Multi-Processor Systems on Chip
TLM Functional Verification and Interface to Metro-II
Using Defect-Map Knowledge for More Efficient Coding [ edit ]
Collaborative Radio Project Update [ edit ]
Perturbation Based Computing
Imperfection-Immune Carbon Nanotube FET Circuits
MetroSPICE++ Core Update
Core Theme Overview and Design Flow
System-Level Modeling II (Routers)
MC-Sim: an Efficient Simulation Tool for Heterogeneous Multi-core Systems [ edit ]
Energy-Aware Design for 1000 Cores: Exploiting VFIs for NoC-Based Systems [ edit ]
TLM Verification Tool and Interface to Metro-II
Synthesis of Reconfigurable High-Performance Multicore Systems
Modeling and Metrics Initiative: In Search of Common Ground
Resilient System Design Theme: Surviving In the Silicon Jungle
Exploiting the Synergy Between Fault Tolerance, Manufacturing Test and Debug [ edit ]
The Importance of Test [ edit ]
CrashTest: Resiliency Analysis Framework [ edit ]
Metrics for Architecture-Level Lifetime Reliability Analysis [ edit ]
Models and Metrics for Test
SymPLFIED: Symbolic Program Level Fault Injection and Error Detection Framework
Reliability Modeling and Simulation for Nanoscale Design
NBTI Induced Performance Degradation in Logic and Memory Circuits: How Effectively Can We Approach a Reliability Solution? [ edit ]
Specification Based Testing vs. Fault Based Testing: Dilemma for Low Cost Testing of Mixed- Signal and RF Circuits
GSRC Workshop: Workloads of the Future [ edit ]
NVIDIA GPU Computing [ edit ]
Workloads of the Future
Future Workloads for Designing Future Computers
Print Workload [ edit ]
NERSC Workload Analysis [ edit ]
Where are Internet workloads going? [ edit ]
Workloads of the Future: "Mobility, Community, Serendipity" [ edit ]
Connecting the Unconnected: the networking challenge
Remarks on Workloads of the Future [ edit ]
High Performance Buildings (Systems) (...and Power...) Challenges for Embedded Systems & Enabling Opprotunities for GSRC
Theoretical Foundations (Alternatives subtheme)
Communication Fabrics
Exploring Network Properties of Oscillators Slides in PDF
Embedded Computer Vision: Challenges and Opportunities Slides in PDF
Accelerating Support Vector Machine Training and Classification Slides in PDF
Spatially Aware Services Applications on Future Generation of Handsets Slides in PDF
Star Challenge -- A real-world computer vision task which requires large amounts of computation power Slides in PDF
Domain-Specific Power-Efficient Computing Slides in PDF
Hard Threads and Liquid Threads: Managing Processing Resources in a Manycore System Slides in PDF
Design Principles for Perturbation Based Computing
Numerical Simulation of Coupled Oscillator Networks
Implementing Carbon Nanotube Transistors in SPICE++ Prototyping Environment
Error Resilient Low-Power Viterbi Decoders
Novel Circuit Fabrics for Networked Computation
Sensor Networks-On-Chip
Misaligned-Carbon-Nanotube-Immune Logic Structures and Metallic-Carbon-Nanotube-Tolerant Circuits
TLM Generation and Verification
MCSim: An ASPN Simulator
Pattern-Based Behavior Synthesis
Stochastic Communication: Modeling, Analysis and Optimization
Optimizing System Performance by Leveraging Local Intra-Core Information
Run-time Resource Management for NoCs with Multiple Voltage Levels
Performance, Energy, and Fault-tolerance Issues in NoC Design Slides in PDF
Synthesis of Reconfigurable High High-Performance Multicore Systems
