Scalable Process Address Space Management
Stochastic Sensor NOC
Fine-Grained Decay-Based Capacity Management For Shared CMP Caches
Parallelizing Implicitly Parallel Applications for Commodity Multicore Systems [ edit ]
Soft NMR
System-level ISA
A MEMS Filter Bank Receiver [ edit ]
Development of a Building Operating Platform [ edit ]
Efficient Test Strategies for Digitally-Calibrated Designs: An ADC Case Study
CMP Architectures with Emerging 3D and Non-Volatile Memory Technologies
Scalable HMM based Inference Engine in Large Vocabulary Continuous Speech Recognition
FCUDA: Compilation of CUDA kernels onto FPGA
HADOOP: How About, 'Don't Overburden Our Powerplants?' [ edit ]
YENSS: Fast Estimation of SRAM/Oscillator Yield Due to Parameter Variability
Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in CMPs
Low Overhead Time-Multiplexed Online Checking: A Case Study of an H.264 Decoder
ManiMOR: Nonlinear Model Order Reduction via Projection on Nonlinear Manifolds
Scheduling for Power, Performance and Reliability
Damascene: Highly Parallel Image Contour Detection [ edit ]
Gen-Adler: Generalized Adler Equation
Using Concurrency to Check Concurrency: Checking Serializability in Software Transactional Memory
Cache Sharing Aware Computation Distribution and Scheduling for Multicore Systems
Coupled Oscillator Simulation
Error-Resilient Low-Power Viterbi Decoders
FTGen: An Automatic Fault Tree Generation Tool for the Design and Analysis of Fault Tolerant Architectures
Living with Uncertainty: The Quest for Fault-Tolerant Networks-on-Chip Communication Protocols
Low Power Robust System Design through Unequal Error Protection, Voltage Over-Scaling & Adaptive Quality Tuning [ edit ]
BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient Search
Verification Guided Error Resilience
Improved On-Chip Router Performance, Power and Area Modeling
CASP: Concurrent Autonomous Chip Self-Test and Diagonstics Using Stored Test Patterns [ edit ]
Integrated Processor-Cache Partitioning in CMPs
Application Aware SoftWare Anomaly Treatment [ edit ]
Sense Amplifier-based Pass Transistor Logic
MSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicore [ edit ]
Analog Platform-based Design
Digitally Assisted Built-in Tuning of RF Systems
PetaBricks: A Language and Compiler for Algorithmic Choice [ edit ]
Distributed Flit-Buffer Flow Control for Networks-on-Chip [ edit ]
Connectivity Brokerage: From Coexistence to Collaboration [ edit ]
CTC End-to-End Flow Control for Networks on Chip
Joint Resource Management for QoS in Many-Core Chips [ edit ]
Specification and Encoding of Transaction Interaction Properties in Transaction-Based Models
An Approach to Energy-Performance-Reliability Tradeoff for On-Chip Network Synchronizations
Brain Machine Interfaces
Identifying critical instructions in programs
Run-Time Energy Optimization for Networks-on-Chip
ADAPT: An Automated Doubly Adaptive Performance Modeling Tool for GPU Architectures
Exploiting Asymmetric Parallelism with DSWP
StageNet: An Adaptive CMP System for Wearout Tolerant Computing [ edit ]
Modeling Yield, Cost, and Quality of a Spare-enhanced Multi-core Chip
ACES: Application-specific Cycle Elimination and Splitting for Deadlock-free Routing on Irregular NoC
Error Resilient System Architecture (ERSA)
Efficient Coding Techniques for Defect Tolerance in Future Nano-Circuits
Phoenix Rebirth: Scalable MapReduce on a NUMA System [ edit ]
Alternate Approach to SSNOC: Outlier Detection
Modeling Energy-Error Behavior for Stochastic Sensor Network-on-Chip Applications
Application Specific Processor Network Synthesis
An Approach to Model Order Reduction for Nonlinear Dynamical Systems in a General Nonlinear Projection Framework
Oscillator Networks and Synchronization
Yield and Cost Modeling of a Spare-Enhanced NoC
Verfication Guided Error Resilience (VGER)
Connectivity Broker For Reliability in Wireless
Pervasive Embedded System for Health Monitoring and Diagnosis
Variation Resilient Spin Torque Transfer MRAM [ edit ]
ElastIC Based Network-on-Chip
Compiler-Driven Speculative Parallelization on Commercial HW
Semantics-Preserving Automatic Code Generation of Synchronous Reactive Communication [ edit ]
Sparing and Routing for Performance Variability and Fault Tolerance
Adaptive Set Pinning: Managing: Managing Shared Caches in CMPs
Verification-Guided Error Resilience
Extending Open Core Protocol to support System-Level Cache Coherence [ edit ]
FPGA Prototyping of Stochastic SNOC
Toward Optimal Sound Reproduction: Closing the Acoustic Loop
Leveraging Local Intra-Core Information to Increase Global Performance in Block-Based Design of Systems-on-Chip
Unlocking the Potential of Automatic Parallelization
Modeling of Complex Bus Architectures: Enabling Heterogeneous Network Synthesis
Voltage-Scalable Error Resilient Microarchitecture
An End-to-end Approach for the Automatic Derivation of Application-Aware Error Detectors
The Cognitive Radio Test Bed [ edit ]
SSNOC Test Chip in 90nm CMOS with Distributed Synchronization
Application Aware Adaptation of Wireless Systems : Image Processing
Performance Analysis for On-Chip Stochastic Communication
PriM: Modeling for Verification
Full-System Chip Multiprocessor Power Evaluations Using FPGA-Based Emulation
Formal Verification of Microprocessors: One Step Closer to Hardware Designers
Runtime Validation of Hardware Transactional Memory Systems
Automating Generation of Verification Tasks
SymPLFIED: Symbolic Program Level Fault Injection and Error Detection Framework [ edit ]
Partition Algorithms for Parallelizing Post-Layout Timing Optimization
Vicis: A High Reliability NoC Router
RAMP Blue: Architecture, Implementation and RDL [ edit ]
Communication Synthesis Infrastructure
Circuit Aging Analysis under NBTI Effect
RAMP Gold Outline Platform and Architecture [ edit ]
EVM Testing of Wireless OFDM Transceivers Using Intelligent Back-End Digital Signal Processing Algorithms
SWAT-Sim: Accurate Microarchitecture-Level Fault Models [ edit ]
RAMP Description Language RDL Overview and Timing [ edit ]
Fast SVM Training and Classification on a GPU
CoSMa: Post-Silicon Verification for Cache Coherence
Design Paradigm for Low Power, Variation Resilient Systems using Adaptive Quality Modulation: Color Interpolation
A MEMS Filter Bank Receiver
SWAT: Hardware Reliability through Software Anomaly Treatment [ edit ]
Task Management for Cache Incoherent Accelerator Architectures
Operating System Support for Parallel Applications on Manycore Platforms [ edit ]
Self-Healing Transceiver Design: Low Cost Built-in Test and Control Driven Simultaneous Tuning of Multiple Performance Metrics
Pattern-Based Behavioral Synthesis and ASIP Synthesis
MCjammer: Adaptive Verification for Multi-core Designs
Portable Parallel Programming with MCUDA
Digitally-Assisted Production Testing of a Digitally Calibrated RF Receiver
Guided Probabilistic Error Compensation for Voltage Overscaled Low-Power Digital Filters
ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration
Time-Multiplexed Online Checking: Resilient Design for Cost-Sensitive SoCs
Design Paradigm for Low Power, Variation Resilient Systems using Adaptive Quality Modulation
SRAM power optimization framework: a reliability perspective
Energy-Aware Design of Networks-on-Chip
CrashTest: a Fault Analysis Platform [ edit ]
Development, Management, and Deployment of Synthetic Biological Systems Using Standardized Parts [ edit ]
CrashTest’ing SWAT [ edit ]
On-Line Circuit Reliability Monitoring
Adaptive Precision Arithmetic (APA) for Error Tolerant Applications
A Flexible 3D Communication Architecture for Media Mining Applications
A Cost Analysis Framework for Multi-core Systems with Spares [ edit ]
Data Parallel Large Vocabulary Continuous Speech Recognition on Graphics Processing Unit
Numerical Simulation of Coupled Oscillator Networks
Implementing Carbon Nanotube Transistors in SPICE++ Prototyping Environment
Error Resilient Low-Power Viterbi Decoders
Novel Circuit Fabrics for Networked Computation
Sensor Networks-On-Chip
Misaligned-Carbon-Nanotube-Immune Logic Structures and Metallic-Carbon-Nanotube-Tolerant Circuits
TLM Generation and Verification
MCSim: An ASPN Simulator
Pattern-Based Behavior Synthesis
Stochastic Communication: Modeling, Analysis and Optimization
Optimizing System Performance by Leveraging Local Intra-Core Information
Run-time Resource Management for NoCs with Multiple Voltage Levels
Design Principles for Perturbation Based Computing
